Designing the Next Generation of Trapped-Ion Quantum Systems

At a Glance

The Challenge

Bright-field microscope image of the foundry-fabricated ion trap chip used in the standing-wave EIT cooling experiment, showing the integrated grating couplers, DC and RF electrodes, and ITO-shielded optical windows. The single ⁴⁰Ca⁺ ion is confined 50 μm above this surface by DC voltage sets calculated in Nullspace ES.

Adapted from Xing et al., arXiv:2512.10900 (2026), Fig. 1d. 

The chip above is the physical heart of the Mehta group's experiment. It integrates six wavelengths of laser delivery, dozens of trap electrodes, and the optical structures needed to confine and manipulate a single calcium ion 50 μm above its surface — all visible in the bright-field photo of the trap zone.

Devices like this push every dimension of trapped-ion engineering at once. Coherent control, low-noise confinement, optical addressing using photonic delivery integrated directly into the trap device, and motional control all have to work together inside increasingly complex chip-scale devices. 

These integrated devices push the limits of what electrostatic simulation needs to deliver. DC voltages applied to trap electrodes have to confine ions, control motional mode orientations, and position single atoms within optical fields to nanometer precision - all within a complex 3D geometry of patterned metal electrodes, dielectric layers, and integrated waveguide structures. Cycle time matters too: each design iteration depends on running a new simulation, and slow tools mean slow research.

Why Nullspace ES

Before adopting Nullspace ES, the Mehta group used a combination of off-the-shelf and in-house tools - and ran into limits with both. They used COMSOL and a Python-based toolkit. COMSOL's comprehensive physics modeling came with longer computation times, while the Python toolkit calculated the analytical solution with a gapless approximation.

The two failure modes capture a tension the group had to resolve: general-purpose tools like COMSOL were accurate enough but too slow to support the experimental cadence; lightweight in-house tools were fast but missed physical features that mattered at the precision the group needed.

Nullspace ES addressed both. To integrate it cleanly into their broader chip design workflow, the group went a step further and built an open-source Python package - trap_sim_nullspace - that ingests GDS chip layout files directly, pre-processes the geometry, automatically generates Nullspace input decks for field simulation, and post-processes the output for analysis. The result is a fully automated pipeline from chip design to experimentally-usable voltage sets.

How Cornell Researchers are Using Nullspace ES

Layout of the trap zone used along with the freespace and integrated optical waveguide and grating elements at the indicated wavelengths, B-field orientation, top metal, and ITO features. Adapted from Xing et al., arXiv:2512.10900 (2026), Fig. 1c. 

The schematic above shows the trap zone layout - the surface electrodes, integrated optical channels, and the ion location 50 μm above the chip. Nullspace ES simulates the electrostatic field from the surface electrode geometry, which the group uses to calculate the DC voltage sets that confine and position the ion.

In the standing-wave EIT cooling experiment, those voltage sets enabled three capabilities critical to the result.

Axial confinement. Trapping single ⁴⁰Ca⁺ ions 50 μm above the surface of a foundry-fabricated trap chip with integrated UV-to-near-IR photonic delivery.

Radial mode rotation. Applying asymmetric DC voltage sets to rotate the orientations of both radial motional modes by 45°, allowing a single standing-wave field to simultaneously cool both modes - a key requirement for the broadband cooling demonstrated in the paper.

Sub-micron ion positioning. Translating the ion through the standing-wave intensity profile with the precision needed to characterize the node-to-antinode response, and to position the ion at the SW node where carrier coupling is suppressed.

The team's results required positioning stability at the ~20 nm level. As Jack describes the workflow: the voltage sets solved by Nullspace provide the baseline, and the team fine-tunes empirically in-experiment to account for stray fields difficult to capture in simulation.

The Result

The Mehta group's experiment is the first experimental demonstration of standing-wave electromagnetically-induced-transparency (EIT) cooling for trapped ions - a scheme rooted in theoretical predictions going back to Cirac et al. (1992) and refined in more recent work.

The chart below shows the cooling trajectories for all three motional modes — black curves for the new standing-wave (SW) scheme, pink for the conventional running-wave (RW) approach. The standing-wave curves drop faster and reach lower phonon numbers across all three motional modes simultaneously, with the largest gains in the radial modes.

Measured phonon number versus cooling time for the radial R1, R2, and axial motional modes, comparing running-wave (RW) EIT cooling and standing-wave (SW) EIT cooling. Both schemes use cooling parameters optimized for R1. The SW scheme reaches a lower final phonon occupancy (n̄ ≈ 0.05) in approximately a third of the time, and simultaneously cools all three motional modes — an architectural advantage enabled by carrier nulling at the SW node. Adapted from Xing et al., arXiv:2512.10900 (2026), Fig. 5a. 

Using integrated UV photonics to deliver phase-stable standing-wave fields, the team cooled motional modes spanning a ~5 MHz bandwidth from the Doppler limit to near the ground state in just 150 μs. Direct comparison with the conventional running-wave approach confirmed that the standing-wave scheme is simultaneously faster, broader in mode bandwidth, and reaches lower final phonon numbers - exactly as predicted by theory.

For trapped-ion quantum computing architectures, where repeated ground-state cooling can dominate total runtime, this is a meaningful step toward faster, broader, and deeper laser cooling from a single integrated drive field.

What's Next

Ion transport - moving ions between zones of a chip-scale trap - is a central capability in QCCD architectures for scalable trapped-ion quantum computing. It requires solving voltage sets dynamically along the trajectory of motion, a substantially heavier computational problem than the static voltage sets used for confinement.

The Mehta group is now extending their Nullspace-based pipeline to support this regime, and is working with the Nullspace team on scaling simulation performance accordingly.

About the Nullspace Academic Program

Nullspace ES is the only commercial electrostatic solver purpose-built for the design of modern ion trap systems and other large-scale electrostatic structures. The Nullspace Academic Program supports leading research groups working on the most demanding simulation problems in quantum computing and electromagnetics.